1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of forming the gate electrode of a complementary MOS device with a p-n gate.
2. Description of the Prior Art
As semiconductor integrated circuits are constantly being reduced in sizes and increasing densities, the design rule is also gradually becoming small, and it will be soon on the order of quarter micrometer (quarter .mu.m: 0.25 .mu.m). Conventionally, an n.sup.+ -type gate is employed for the gate electrode of a complementary MOS device (to be simply referred to as a CMOS hereinafter): an nMOSFET or a pMOSFET.
This n.sup.+ -type gate is formed by, e.g., diffusing phosphorus immediately after a polysilicon film deposition. When the n.sup.+ -type gate is to be employed for a pMOSFET, the manufacturing process can be shortened although there is a serious problem that the threshold voltage largely varies in respect to the variation in gate length. When the gate length was larger than the quarter micrometer, the variation of threshold voltage corresponding to the variation of gate length due to manufacturing variations could be managed by keeping the threshold voltage of the transistor somewhat high because the power supply voltage was relatively high.
However, in quarter micrometer CMOS, the power supply voltage is generally 2.5 V or less, and the threshold voltage of the transistor must be lowered. If the n.sup.+ -type gate is employed for a pMOSFET, the threshold voltage does not stabilize and cannot guarantee the stability of circuit operation, resulting in a decrease in manufacturing yield.
As the gate electrode structure of a CMOS, a p-n gate is becoming the mainstream: an n.sup.+ -type gate for an nMOSFET, and a p.sup.+ -type gate for a pMOSFET. The n.sup.+ - and p.sup.+ -type gate electrodes are generally formed simultaneously with formation of n.sup.+ - and p.sup.+ -type diffusion layers by ion implantation. Tungsten polycide which is conventionally used to lower the resistance of the gate electrode cannot be used as the p-n gate. Because the tungsten polycide enhances lateral diffusion of impurities at source/drain activation. The lateral diffusion causes the variation of the threshold voltage. Generally, after n.sup.+ - and p.sup.+ -type gate electrodes and diffusion layers are formed, the gate electrodes and diffusion layers are salicided by titanium or cobalt.
However, this p-n gate also has two problems: I)boron penetration through the gate oxide at the source/drain activation, which causes a variation of the threshold voltage. II)the low gate yield of pMos that is caused by a destruction of the gate oxide, and this is a serious problem for the semiconductor device. It has been reported that the gate yield is related to the boron penetration.
In order to eliminate the boron penetration, a gate electrode structure with at least two polysilicon layers which are formed by different process conditions has been proposed, as disclosed in Japanese Unexamined Patent Publication No. 6-296016. According to an embodiment described in Japanese Unexamined Patent Publication No. 6-296016, after a first polysilicon film is deposited, ion implantation is performed to adjust the threshold value, and then, a second polysilicon film is deposited by a method that differs from one for the first polysilicon deposition. The gate electrode consists of two polysilicon layers with different crystal structures and it prevents boron channeling at source/drain implantation.
However, this method has some problems. Since the ion implantation for the adjustment of threshold voltage is performed through the gate oxide film, the gate oxide film is inevitably damaged. As a result, the reliability of the gate oxide degrades. It is a serious problem for semiconductor devices. In addition since the ion implantation for the adjustment of threshold voltage is also performed through the first polysilicon film, the ion implantation energy must be inevitably made higher. The impurity profile has a long tail. As a result, the junction capacitance. Furthermore, to form at least two polysilicon films by different deposition methods, a plurality of furnaces must be prepared. Alternatively, if only one furnace is to be used, the film formation conditions such as the temperature and source materials must be changed for each film. Therefore, the cost increases, or the manufacturing yield lowers unavoidably due to generation of particles.
The degradation of the pMOS yield as the second problem is conspicuous when the gate electrode material is polysilicon.
The present inventor has examined a technique of implanting phosphorus in polysilicon in advance, as disclosed in Japanese Unexamined Patent Publication No. 5-218436. This technique could improve the gate yield to some extent but was not perfect.
Next, as disclosed in Japanese Unexamined Patent Publication No. 6-326304, studies have been made using phosphorus-doped amorphous silicon as a gate electrode material. The yield of pMOSs whose gates have the rated breakdown voltage greatly increased, as shown in FIGS. 1A and 1B. Is was also confirmed that the phosphorus-doped amorphous silicon could suppress boron penetration in annealing. However, when a CMOS device was manufactured using the phosphorus-doped amorphous silicon as a gate electrode material, an anomalous hump appeared in the subthreshold characteristics of an nMOSFET with a gate length of 0.5 .mu.m or less, as shown in FIG. 2. The reason for this is as follows. Large columnar grains having a height corresponding to the film thickness are grown when crystallizing the phosphorus-doped amorphous silicon film. At source/drain implantation, the arsenic channeling occurs in the grains with the lattice orientation in which the channeling is likely to occur. The a local variation in the concentration of surface impurities occurs. As a result, the hump appears in the subthreshold characteristics.
Plane TEM observation of the phosphorus-doped amorphous silicon film revealed that the grain size was about 0.5 .mu.m. As described above, the subthreshold characteristics of an nMOSFET with a gate length of 0.5 .mu.m or less have a hump. This has a close relation to the grain size, and it can be explained that when the grains in the gate electrode become a bamboo structure, a hump appears in the subthreshold characteristics.
The first problem in the CMOS using the p-n gate is that, in the prior art, the gate of pMOS degrades. The reason for this is related to boron penetration through the gate oxide film.
The second problem is that a hump appears in the subthreshold characteristics when the phosphorus-doped amorphous silicon is used for the improvement of the pMOS gate yield.
The reason for this is as follows. At source/drain implantation, the arsenic channeling occurs in the grains with the lattice orientation in which the channeling is likely to occur. Then, a local variation in the concentration of surface impurities occurs. As a result, the hump appears in the subthreshold characteristics.